1. Field of the Invention
The invention relates to the field of electrically programmable and electrically erasable metal-oxide-semiconductor (MOS) memory cells.
2. Prior Art
Numerous read-only memories employing floating gate memory cells are well-known and commercially available. Typically, these memories are fabricated with MOS technology. Each cell includes a polycrystalline silicon (polysilicon) floating gate which is completely surrounded by insulation such as silicon dioxide. Various mechanisms are used to transport charge onto the floating gate and to remove the charge from this gate. In one class of memories (EPROMs), charge is transported to the floating gate through channel injection or avalanche injection and is removed by exposing the memory to ultraviolet radiation. More recently, memories have become available which may be electrically programmed and electrically erased (E2PROMs). Currently, the most successful commercial version of this memory employs a thin oxide region. Charge is tunelled onto and from the floating gate through this thin oxide region. This cell (which includes a selection transistor and E2device) is described in U.S. Pat. No. 4,203,158. Memory circuits for using these cells in an arrangement which permits erasing of single words in an array is described in U.S. Pat. No. 4,266,283.
There are a number of difficulties with the prior art cell which are overcome by the present invention. First, to program the E.sup.2 device, relatively large capacitive coupling is required between the floating gate and the overlying control gate. This coupling is necessary to obtain a sufficient field at the thin oxide region to tunnel charge onto the floating gate from the substrate. To obtain this coupling, relatively large areas are required between the floating gate and the overlying control gate. Secondly, in a typical memory array using E.sup.2 devices such as the Intel 2816, selection device (a field-effect transistor) is coupled in series with each E.sup.2 device. The selection device is used to isolate the E.sup.2 device when, for instance, neighboring devices are being read. During the reading of data in a memory cell, a potential is applied to the control gate of the cell. While this potential is substantially less than the porgramming potential, nonetheless, some slow programming can occur because of the large capacitive coupling discussed above. The selection device is used to isolate the cells and prevent this slow programming. This selection device; however, is mainly required to isolate the E.sup.2 device during programming.
As will be seen with the present invention, a different mechanism is used to program the E.sup.2 devices, permitting the capacitive coupling between the control gate and floating gate to be reduced and consequently the substrate area required for each cell may be decreased. Also, since this coupling is reduced, the slow programming problem described above is greatly lessened, making possible single device E.sup.2 cells, that is, cells without the selection devices.
A new mechanism for charging particularly EPROM cells has recently been discovered. With this mechanism, excess charge such as electrons are injected from a junction or other source into a substrate. The potential on a control gate and source/drain terminals of a memory cell causes these excess electrons to accelerate toward the interface between the floating gate and substrate. Some of the electrons gain sufficient energy to surmount the barrier and are injected through the oxide separating the floating gate and substrate, remaining trapped on the floating gate. One advantage to this technique is that a single source of electrons or other charge may be shared by a plurality of cells. This technique allows the reduction in cell geometry and reduction in programming potentials.
There has been some discussion of using this "excess charge" technique for programming E.sup.2 devices. However, it had previously been believed that charge should be removed from the floating gate through avalanche injection employing a series of pulses. The advantages to be gained by the present invention when using tunnelling for removing the charge was not understood or recognized.
This injection technique is described in British Patent Application No. 8233041, filed Nov. 19, 1982.